A JTAG (Joint Test Action Group) bus (or a JTAG interface) connected to an LSI device may be mounted on a system as a board, a unit or a module with a large scale integrated circuit (LSI) device or a chip mounted thereon. The JTAG bus may be used for performing a test of the LSI device. The JTAG bus is a serial bus and may conform to a global standard such as IEEE1149.1, which enables a test of an LSI device at the test time other than the time of operating a system by providing an access to the LSI device from an external tester for performing a boundary scan on the LSI device.
On the other hand, there are some LSI devices including an I2C (Inter-integrated Circuit) bus (or an I2C interface) and an SM Bus (System Management Bus) (or SM Bus interface) connected, in the LSI device group such as a device, a chip set or a central processing unit (CPU) used for a system. The I2C bus and the SM Bus may be used when performing various controls in the system at the operating time. One system may have an LSI device connected to the JTAG bus, and another r LSI device connected to the I2C bus or the SM Bus. In other words, such system may include a mixture of LSI devices connected to different types or standards of buses and one LSI device may be connected to the different types (or standards) of the buses. The I2C bus and the SM Bus are general communication buses between devices or chips. The I2C bus and the SM Bus are serial buses of two wires including a clock signal wire and a data signal wire and the device connected to the serial bus has its specific address. By use of this address, the devices may communicate with each other through the I2C bus and the SM Bus.
In scanning a command register and a data register in the LSI device at a time of operating a system, only one chain or one path carrying out the scan at once may exist. Therefore, scanning of the LSI device for the number of times corresponding to the product of the number of chains and the number of latches may be necessary in collecting a plurality of chain settings and logs. In a uni-chain mode of connecting internal chains in a series, performing of a scan for the number of latches may be necessary. In collecting a plurality of chain settings and logs, the number of the times of scanning the LSI device increases, thus increasing the scan time required for scanning.
Conventionally, a e method of scanning a circuit such as the LSI device includes that at a time of operating a system, since a collection of a plurality of chain settings and logs may be necessary in starting up the system at the power-on, collecting logs, and changing the mode of the system. Thus, the necessary number of the times of scanning the LSI device increases enormously. Therefore, it has been hitherto difficult to shorten the scan time, the time for starting up a system, the time for collecting logs, and the time for changing a mode.